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general description gd16585 and GD16589 are transmitter chips used in sdh stm-64 and sonet oc-192 optical communication systems. the device is available in two versions: gd16585 for 9.5328 gbit/s. GD16589 for 10.66 gbit/s with forward error correction (fec). except the different operating bit rate the two versions are functional identical. the transmitter integrates the main func - tions of the serializer which are: clock multiply unit (cmu) 16:1 multiplexer in a single monolithic ic. the cmu consists of phase locked loop (pll) controlled from an external reference clock. the pll characteristics are controlled by an external loop filter al- lowing the user to optimize the jitter perfomance of the device. the 16:1 multiplexer accepts 16 parallel input bits at 622.88 mbit/s (or 666 mbit/s) that are serialized into a 9.9538 gbit/s (or 10.66 gbit/s) data stream. the serialized data stream is re-timed by the high- speed clock from the vco. the parallel input interface features giga?s unique self-synchronizing dy - namic phase alignment scheme that al - lows both: source synchronous counter clocking for oif99.102.5 interfaces. forward clocking with phase nulling and jitter clean-up of the clock. these schemes enable the serializer to absorb output delay variations from the upstream system asic without use of initialization or reset. the data and clock inputs to the mux are lvds and the output data is cml compatible. the device operates from a dual -5.2 v and +3.3 v power supply. the power dis- sipation is 2.2 w, typical. the device is manufactured in a silicon bipolar process and packaged in an 132 balls 13 13 mm ceramic/plastic ball grid array (cbga). an intel company data sheet rev.: 13 preliminary features pll based cmu with on-chip 10 ghz or 10.66 ghz vco. 16:1 multiplexer with a last stage re-timing. oif99.102.5 compliant timing . lvds compatible parallel data and clock inputs cml compatible serial data output. 155 mhz or 622 mhz reference clock input (selectable). divide by 16 clock output. pll out of lock detector. dual supply operation: -5.2 v and +3.3 v low power dissipation: 2.2 w (typ.). available in three package versions: ? eb: 132 ball (16 mill) ceramic bga1313mm ? ef: 132 ball (20 mill) ceramic bga1313mm ? fb: 132 ball (20 mill) plastic bga1313mm available in two versions: ? gd16585 for 10 gbit/s ? GD16589 for 10.66 gbit/s applications telecommunication systems: ? sdh stm-64 ? sonet oc-192 ? optical transport networking (otn) ? fec applications fibre optic test equipment. 10 gbit/s transmitter mux with re-timing gd16585/GD16589 (fec) out vdd vcc vddo vdda vee timing control pfcx phase selector vco 16:1 multiplexer phase frequency detector sel3 refck/n sgnx pctlx din15 sel1 sel2 ckin ckoutn ff din0 di15 cki ckout di0 outn nldet pctl vctl (phigh) (plow) tck vcur parallel input data
functional details the main function of gd16585/GD16589 is as transmitter in stm-64 /oc-192 and otn optical communication systems. it integrates: voltage controlled oscillator (vco) phase and frequency detector (pfd) 16:1 multiplexer re-timing of output data. phase nulling circuit for interfacing in - put data and clock. vco the vco is an lc-type differential oscil - lator controlled by pin vctl and with a tuning range of 5 %. the vco and the clock divider circuit generate the clock signals and load pulses needed for multiplexing and timing control. with the vctl voltage at -3 v the vco frequency is fixed at 9.953 ghz (for gd16585) and by changing the voltage from 0 to ? 5.2 v the frequency is con - trolled from 9 ghz to 10.2 ghz. the modulation bandwidth of vctl is 90 mhz. the reference clock the pfd is made with digital set/reset cells giving it a true phase and frequency characteristic. the reference clock (refck/refckn) to the pfd is 155 or 622 mhz selectable by sel3. the reference clock input is a cml input with 50 internal termination resistors. the reference clock should be used dif - ferential for obtaining lowest clock jitter. the pll synchronizes the vco to the external reference clock. spectral noise from the reference clock, within the pll bandwidth, will be multiplied and added to the serial output by the divider ratio between the vco and reference clock i.e.n=16orin terms of phase noise as 20log(16) = 24 db (or 36 db a t n = 64). a low noise reference clock with low clock jitter is required in order to fulfill the itu-t jitter requirements. inputs the parallel data (dix/dinx) and clock (cki/ckin) inputs are lvds compatible with internal differential 100 resistors. the set-up and hold time between input clock and data is selectable in four set - tings by sel1-2. the timing relation is oif99.102.5 com - plaint with sel1,2 = 1,1 (0 v). the select inputs (sel1-3 and sgnx) are low-speed ecl compatible inputs, which can be connected directly to the negative supply rails (0 / -5.2 v). bit order the parallel data input is multiplexed with di0 as the first sent bit, di1 as the sec - ond sent bit and with di15 as the last sent bit in a 16 bit frame. note: this bit naming covention is opposite to oif99.102.5 for oif interfaces the data pins should be connected as shown in the following table. input pin: oif: di0/din0 txdata15_p/n (msb) di1/din1 txdata14_p/n di2/din2 txdata13_p/n di3/din3 txdata12_p/n di4/din4 txdata11_p/n di5/din5 txdata10_p/n di6/din6 txdata9_p/n di7/din7 txdata8_p/n di8/din8 txdata7_p/n di9/din9 txdata6_p/n di10/din10 txdata5_p/n di11/din11 txdata4_p/n di12/din12 txdata3_p/n di13/din13 txdata2_p/n di14/din14 txdata1_p/n di15/din15 txdata0_p/n (lsb cki txclk_p ckin txclk_n loop filter for the cmu an external passive loop filter is used, consisting of a resistor and a capacitor driven from the pctl pin, which outputs the phase and frequency information from the pfd. the values of the external components determines the characterisitcs of the pll e.g. bandwidth and transfer function. for recommended loop filter values see figure 1 . the pcb layout of the loop filter and the connecting lines between pctl and vctl are critical for the jitter perfor - mance of the device. the external com - ponents and the artwork should be placed very close to the pins at gd16585. if the phigh and plow outputs are not used they must be shorted to vdd (0 v), please refer to figure 1 . the outputs the output of the mux stage is retimed by the 10 ghz (or 10.66 ghz) clock and the output driver is a current mode logic (cml) output with internal 50 termina - tion resistors. the serial output driver is internally termi - nated with 50 resistors to 0 v. the out - put should be terminated externally with 50 at the receive end and should be used differential. both out and outn are best terminated with the same load resistor e.g. 50 , an asymmetric loading will decrease the performance of the out- put due to reflections. both outputs out/outn are not esd protected and extra precautions should be taken when handling the outputs (the internal 50 resistor provides some esd hardness making the ouput low impedance). a divide by 16 clock output from the cmu is available at ckout/n for jitter measurement and test purpose. these outputs are differential open collector witha8ma output current. they are ter - minated externally with resistors and can be terminated to the positive 3.3 v supply. the clock outputs should be ter - minated even though they are not used. pll out of lock detect signal (nldet) is provided as a status signal of the pll. it compares the vco clock with the refer - ence clock and is low whenever the vco is locked to the reference clock. the nldet is an open collector output and must be terminated by an external resis - tor. the output voltage control the serial output voltage swing at out/outn is controlled by vcur in the range from 0.1 v to 0.8 v. the voltage swing is increased by increasing the vcur voltage and the output is off at voltages below vee +2 v. data sheet rev.: 13 gd16585/GD16589 page 2 of 17
if no adjustement is needed the vcur can be lefted open. with ac coupled outputs the vcur pin must not be directly connected to 0 v which may cause the output stage to saturate deteriorating the eye-diagram. refer to figure 1 for the recommended set-up of vcur. timing to the system asic the component supports source synchronouse clocking for oif99.102.5 interface (311 mhz clock mode is not supported) and forward clocking with phase nulling and jitter clean-up of the reference clock. with a oif interface a phase adjusted source clock is feed back to the system asic and data and clock are feed forward to the high-speed mux. the phase difference between the for - ward clock (cki/ckin) and the internal load pulse is detected by the phase and frequency detector (pfcx) and the phase information (pctlx) are use to control the phase and frequency of the external vcxo (622 mhz). the phase adjusted output clock of the vcxo can be used either as a source (counter) clock to the system asic (oif99.102.5 in 622 mhz clock mode) or as a jitter clean reference clock (refck/n) to the on-chip cmu. the phase information at pctlx is fil- tered in an external low pass filter con- sisting of a capacitor and a resistor. for recommended component values, please refer to figure 1 . package gd16585 and GD16589 are packaged in an 132 ball ceramic/plastic bga (13 13 mm). for the package outline, please refer to figure 14 and 15 . in ceramic packages following pin pairs are individually shorted inside the pack - age and mainly used as power pins: c3/d3, c4/d4, c5/d5, c8/d8, c9/d9, c10/d10, j3/k3, j4/k4, j5/k5, j8/k8, j9/k9, and j10/k10, please refer to ? package pinout ? figure 8 on page 8 . thermal condition the component dissipates 2.2 w with a ? 5.2 v and +3.3 v voltage supply. the die is mounted in a cavity on a metal pad directly connected to the center balls (e4-9, f4-9, g4-9, and h4-9). it is important to have a good thermal connection from the center balls of the package to the ambient environment to ensure the best thermal conditions. note: to obtain t case <70 c, the pgba (compared to the cbga) requires additional cooling on the case, for details, please refer to application note ? pbga - thermal data.... ? . 10.66 gbit/s application a version of the transmitter with a bit rate of 10.66 gbit/s for optical transport net - working (otn) and forward error cor - rection (fec) application is available. the part number is GD16589. the functionality and the pin-out are identically to the gd16585. the center frequency of the vco (10.66 ghz) is the only difference to the gd16585. data sheet rev.: 13 gd16585/GD16589 page 3 of 17
application figure 1. application information, oif interface to the framer. figure 2. de-coupling of the power supply data sheet rev.: 13 gd16585/GD16589 page 4 of 17 out of lock 10gbit/s output ckin din0..15 cki di0..15 vdd/vdda (vddo) framer gd16585/GD16589 0v +3.3v vcc 10nf 16 16 100nf 33nf vdda vdd -5.2v -5.2v -5.2v -5.2v 0v 0v vcc vcc + - 0v 0v 622mhz 155mhz 0v -5.2v 1k 500 330 50 10k 4.7k 2.2k pctlx vco refck refckn nldet sel1 sel2 sel3 sgnx pctl vctl plow phigh ckoutn ckout vcur out outn vee pin d1 pin c2 pin d11 vdd vddo vcc vdda vee vee vdd vee, vcc, vdda pins refer to pin list for all vdd pins refer to pin list pin d2 a7 pin m3 k5 pin j8 pin k8 c cc c ccc c cccccccccc 10f 10 f 10 f c is 10nf parallel with 100pf.
10 gbit/s output interface figure 3. 10 gbit/s outputs (out/outn), dc coupled. figure 4. 10 gbit/s outputs (out/outn), ac coupled. note: with ac coupled outputs vcur must not be connected directly to 0 v. data sheet rev.: 13 gd16585/GD16589 page 5 of 17 gd16585/GD16589 driver 50 msl 50 50 0v -5.2v out outn vcur gd16585/GD16589 driver 50 msl 100nf 50 50 0v -5.2v out outn vcur
622 mbit/s output interface figure 5. open collector output. open collector outputs should always be terminated at the receiver end, by preferably 50 . 622 mbit/s input interface figure 6. lvds compatible input. reference clock input figure 7. reference clock input (refck/refckn), differential ac coupled. data sheet rev.: 13 gd16585/GD16589 page 6 of 17 gd16585 50 50 msl 8ma (0v or 3.3v) -5.2v gd16584 or gd16585 lvds output 50 msl 100 vee (-5.2v) vcc (+3.3v) refck refckn gd16585 50 500 500 100nf 0v 0v -5.2v -5.2v -5.2v
pin list mnemonic: pin no.: pin type: description: di0, din0 di1, din1 di2, din2 di3, din3 di4, din4 di5, din5 di6, din6 di7, din7 di8, din8 di9, din9 di10, din10 di11, din11 di12, din12 di13, din13 di14, din14 di15, din15 c7, d7 a8, b8 a9, b9 b10, a11 c11, c12 d12, e12 g11, h12 j12, j11 l9, m9 l8, m8 l6, k6 m5, l5 m4, l4 l3, m2 k3, l2 l1, k2 lvds in data input, differential 622 mbit/s. multiplexed to serial output starting with di0, di1...di15. note: the bit naming convention is opposite to oif99.102.5: di0 is msb. please refer to item ? bit order ? on page 2. refck, refckn b5, a6 cml in reference clock input, differential 155 mhz or 622 mhz. sel1, sel2 a3, b4 ecl in select the set-up and hold time beetwen the data and clock inputs in four settings. for setting, please refer to figure 13 and table on page 14 . when left open, the inputs are pulled to ? 1 ? (vdd). sel3 a4 ecl in select the reference clock frequency. 0 155 mhz 1 622 mhz when left open, the input is pulled to ? 1 ? (vdd). cki, ckin b6, b7 lvds in data clock input. out, outn h1, e1 cml out data output, differential 10 gbit/s. no internal esd output pro- tection . ckout, ckoutn l12, l11 open collector clock output, differential 622 mhz. always terminate by 50 to vdd. pctl c3 analogue out charge pump output for cmu pll. pctlx a1 analogue out charge pump output from pfcx to external vcxo. (phigh, plow) b3, c4 open collector not used. always terminate to vdd. vctl b1 analogue in vco input voltage control. vcur k1 analogue in output voltage control. nldet c6 open collector no lock detect output. always terminate with a resistor to vdd. sgnx k12 ecl in selects between positive and negative vcxo constant. 0 positive vcxo constant 1 negative vcxo constant when left open, the input is pulled to ? 1 ? (vdd). tck c1 ecl in used for test purpose. connect to vdd. vdd a2, a5, d1-2, d6, e4-9, f1-2, f4-9, f11, g1-2, g4-9, h4-9, j1-2, j6, j8, k8 pwr digital ground 0 v. vdda a7, c5 (d5), j5 (k5) pwr pll ground 0 v. vddo c2 pwr vco ground 0 v. for test purpose connect to vee. data sheet rev.: 13 gd16585/GD16589 page 7 of 17
mnemonic: pin no.: pin type: description: vee b2, c8, c10, d8, d10, j4, j9, k4, k9 pwr -5.2 v digital supply voltage. vcc d11, j7, j10 (k10), m3 pwr +3.3 v supply voltage for lvds i/o. nc a10, a12, b11-12, c9, d9, f12, g12, k7, k11, l7, l10, m1, m6, m7, m10-12 not connected. reserved for future use. nc d3-4, j3 do not connect. package pinout figure 8. packages eb and ef pinout. top view seen through the package. data sheet rev.: 13 gd16585/GD16589 page 8 of 17 123456789101112 xxx xxx a b c d e f g h j k l m 123456789101112 a b c d e f g h j k l m pctlx vctl tck outn out vcur di15 nc vdd vddo din15 din14 din13 (empty) = vdd = internally shorted in the package sel1 (phigh) vee pctl nc di14 nc di13 vcc sel3 sel2 (plow) nc vee vee din12 di12 vdd refckn refck vdda vdda vdda vdda din11 di11 cki nldet din10 di10 nc vdda ckin di0 din0 vcc nc nc nc di1 din1 di9 din9 di2 din2 nc vee nc vee vee vee di8 din8 nc di3 vee vee vcc vcc nc nc din3 nc di4 vcc di6 din7 nc ckoutn nc nc nc din4 di5 din5 nc nc din6 di7 sgnx ckout nc
figure 9. package fb pinout. top view seen through the package. data sheet rev.: 13 gd16585/GD16589 page 9 of 17 123456789101112 xxx xxx a b c d e f g h j k l m 123456789101112 a b c d e f g h j k l m pctlx vctl tck outn out vcur di15 nc vdd vddo din15 din14 din13 (empty) = vdd = internally shorted in the package sel1 (phigh) vee pctl nc di14 nc di13 vcc sel3 sel2 (plow) nc vee vee din12 di12 vdd refckn refck vdda vdda vdda vdda din11 di11 cki nldet din10 di10 nc vdda ckin di0 din0 vcc nc nc nc di1 din1 di9 din9 di2 din2 nc vee nc vee vee vee di8 din8 nc di3 vee vee vcc vcc nc nc din3 nc di4 vcc di6 din7 nc ckoutn nc nc nc din4 di5 din5 nc nc din6 di7 sgnx ckout nc
maximum ratings these are the limits beyond which the component may be damaged. all voltages in table are referred to vdd/vdda. all currents are defined positive out of the pin. vddis0vorgnd symbol: characteristic: conditions: min.: typ.: max.: unit: v ee negative supply -6 v v cc positive supply +4 v v i lvds lvds input voltage 0 v cc +0.5 v i i lvds, cml lvds and cml output current note 1 -24 24 ma v i cml cml input voltage v ee +3 0.5 v v o cml cml output voltage v ee +3 0.5 v v esd static discharge voltage hbm, note 3 500 v cdm, note 4 50 v t j junction temperature note 2 -55 +125 o c t s storage temperature -65 +125 o c note 1: nominal supply voltages. note 2: the maximum temperature equals a maximum case temperature of 105 c (top side) with the device mounted on the gd90584/585 evaluation board. note 3: human body model: mil 883d 3015.7 standard. note 4: charge device model.: jesd2-c101 standard. data sheet rev.: 13 gd16585/GD16589 page 10 of 17
dc characteristics t case *=0 cto70 c. vee = -5.2 v. vcc = +3.3 v. vdd i s0vor gnd. all voltages in table are referred to vdd. all currents are defined positive out of pin. symbol: characteristic: conditions : min.: typ.: max.: unit: v ee negative supply voltage -5.46 -5.2 -4.94 v v cc positive supply for lvds i/o +3.135 +3.3 3.465 v i ee negative supply current 400 500 ma i cc positive supply current -21 -17 ma v ih lvds lvds input voltage high, (differential) 100 mv v il lvds lvds input voltage low, (differential) -100 mv v ivr lvds lvds input voltage range 0.8 2.4 v r in lvds lvds input resistor termination dc 80 100 120 v oh oc open collector output voltage high note 1 -0.05 0 +0.05 v v ol oc open collector output voltage low note 1 -0.5 -0.4 -0.3 v i oh oc open output current high note 1 -0.1 0 +0.1 ma i ol oc open output current low note 1 -9 -8 -7 ma v oh out out/outn voltage high note 1, 10 mhz -0.1 -0.05 +0.05 v v ol out out/outn voltage low note 1, 10 mhz -0.8 note 3 -0.7 -0.5 v i oh out out/outn current high note 1 0 ma i ol out out/outn current low note 1 -14 ma v ih sel1-3,sgnx sel1-3, sgnx input voltage high note 2 0 v ee +2 v v il sel1-3, sgnx sel1-3, sgnx input voltage low note 2 v ee v ee + 0.8 v note 1: output externally terminated by 50 to0v. note 2: sel1-3 and sgnx can be connected directly to vdd or vee. note 3: v ol out min. may require vcur adjustment, vcur > -1 v. *: t case measured at the center of the top. data sheet rev.: 13 gd16585/GD16589 page 11 of 17
ac characteristics, general t case *= 0 cto70 c, vee = -5.2 v. vcc = +3.3 v. symbol: characteristic: conditions: min.: typ.: max.: unit: j trf jitter transfer f<8mhz note 1 0.0 0.1 db j gen jitter generation 12 kh zGD16589 635 680 mhz mhz note 1: with the recommended loop filter. note 2: from dc to 6 ghz, measured on the gd90584/585 evaluation board. note 3: the output voltage is adjustable by pin vcur. *: t case measured at the center of the top. data sheet rev.: 13 gd16585/GD16589 page 12 of 17
ac characterisitcs, source synchronous clocking - oif99.102.5 t case *=0 cto70 c, vee = -5.2 v. figure 10. oif interface. figure 11. timing relation between input data and clock. symbol: characteristic: conditions: min.: typ.: max.: unit: t s di0-15 setup sel1 = sel2 = ? 1 ? 125 ps t h di0-15 hold sel1 = sel2 = ? 1 ? 175 ps note: the setup and hold time is defined from the rising edge of cki. the setup time is positive before the edge and the hold time is positive after the edge. *: t case measured at the center of the top. data sheet rev.: 13 gd16585/GD16589 page 13 of 17 txdata txclk txclk_src 155/622 mhz 32 2 2 2 di0..15 din0..15 refck cki refckn pctlx sel1 sel2 ckin -5.2 v framer oif99.102.5 vcxo gd16585 t s t h cki di0-15
ac characteristics, forward clocking to system asic t case *= 0 cto70 c, vee = -5.2 v. figure 12. forward clocking with phase nulling circuit. figure 13. timing relation between input data and clock. symbol: characteristic: conditions: min.: typ.: max.: unit: t s,11 di0-15 setup time (sel1,sel2) = (1,1) 125 ps t h,11 di0-15 hold time (sel1,sel2) = (1,1) 175 ps t s,00 di0-15 setup time (sel1,sel2) = (0,0) 560 ps t h,00 di0-15 hold time (sel1,sel2) = (0,0) -260 ps t s,10 di0-15 setup time (sel1,sel2) = (1,0) 930 ps t h,10 di0-15 hold time (sel1,sel2) = (1,0) -630 ps t s,01 di0-15 setup time (sel1,sel2) = (0,1) 1350 ps t h,01 di0-15 hold time (sel1,sel2) = (0,1) -1050 ps t d delay between cki and ckout tbd ps note: the setup and hold time is defined from the rising edge of cki. the setup time is positive before the edge and the hold time is positive after the edge. sel3 = ? 0 ? *: t case measured at the center of the top. data sheet rev.: 13 gd16585/GD16589 page 14 of 17 txdata txclk 32 2 di0..15 din0..15 refck cki refckn pctlx ckin -5.2 v system asic vcxo gd16585 t s t s t s t s 1,1 0,0 1,0 0,1 t h t d t h t h t h cki ckout di0-15
package outline figure 14. package 132 ball ceramic bga (eb and ef package). data sheet rev.: 13 gd16585/GD16589 page 15 of 17 ef - package
figure 15. package 132 ball plastic bga (fb package). data sheet rev.: 13 gd16585/GD16589 page 16 of 17
device marking figure 16. device marking. top view. ordering information to order, please specify as shown below: product name: version: package type: intel order number: case temperature range: gd16585-eb 10 gbit/s 132 ball (16 mil) ceramic bga hcgd16585eb mm# 835479 0...70 c gd16585-ef 10 gbit/s 132 ball (20 mil) ceramic bga hcgd16585ef mm# 837348 0...70 c gd16585-fb 10 gbit/s 132 ball (20 mil) plastic bga rcgd16585fc mm# tbd 0...70 c GD16589-eb 10.66 gbit/s 132 ball (16 mil) ceramic bga hcGD16589eb mm# 835481 0...70 c GD16589-ef 10.66 gbit/s 132 ball (20 mil) ceramic bga hcGD16589ef mm# 837350 0...70 c GD16589-fb 10.66 gbit/s 132 ball (20 mil) plastic bga rcGD16589fc mm# tbd 0...70 c gd16585/GD16589, data sheet rev.: 13 - date: 14 november 2001 the information herein is assumed to be reliable. giga assumes no responsibility for the use of this information, and all such information shall be at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. giga does not authorise or warrant any giga product for use in life support devices and/or systems. mileparken 22, dk-2740 skovlunde denmark phone : +45 7010 1062 fax : +45 7010 1063 e-mail : sales@giga.dk web site : http://www.intel.com/ixa please check our internet web site for latest version of this data sheet. distributor: copyright ? 2001 giga aps an intel company all rights reserved an intel company gd16585- - GD16589- -

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